With the advent of System on Chip (SoC) designs, the growth of integrated circuit (IC) chip size has reached a level that necessitates automated circuit design assistance employing teams of designers. Each team of designers is typically responsible for independently designing a subsystem of the overall system that requires interfacing with the other subsystems on a hierarchical basis for the chip. In many cases, this hierarchical interfacing currently requires a circuit level determination of the impact of this hierarchical interfacing on the subsystem, thereby slowing the interfacing process and requiring a high level of designer knowledge about the subsystems. Improvements in this area would prove beneficial to the art.